Mapping of cores has been an important activity in NoC-based system design aimed to find the best topological location onto the\nNoC, such that the metrics of interest can be greatly optimized. In the last years, partial reconfigurable systems (PRSs) have included\nNetworks-on-Chips (NoCs) as their communication structure, adding complexity to the problem of mapping. Several works have\nproposed specific and robust NoC architectures for PRSs, forming indirect and irregular networks, in which cases the mapping\nand placement problems must be treated altogether. The placement deals with the physical positioning of those cores inside the\nreconfigurable device. Up to now, to the best of our knowledge, the mapping-placement problem for those kinds of architectures\nhas not been addressed yet. In this work, the problem formalization for the design-time hardware core placement and mapping\nin PRS-NoCs is proposed and methodologies for solving it with genetic algorithms (GAs) are presented. Several GA crossovers\nand methodologies are compared for obtaining the best solution. Results have shown that best GA solution obtained, in average,\ncommunication costs with 4% of penalty when compared with global minimum cost, obtained in a semi exhaustive approach. In\naddition, the algorithm presents low execution times.
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